Your CPU Has More Registers Than You'd Think

Modern CPUs contain far more registers than the architectural registers exposed to programmers. Physical registers (hundreds of them) underpin a hardware mechanism called register renaming, handled by the rename/map unit in the decode stage. The rename unit maps architectural registers (like x0-x31 on AArch64) to physical registers, eliminating false dependencies such as Write-After-Write (WAW) hazards. This enables out-of-order execution and instruction-level parallelism. The post also covers zero-cycle (issueless) instructions — like register moves — that are resolved entirely at the rename stage without consuming execution unit resources, verified using llvm-mca on the ARM Neoverse V2 microarchitecture.