Chronicles of a bad idea. Or how I designed a systolic array with in-silicon debug infrastructure from scratch in under two weeks, and taped it out on Global Foundry 180 nm though a Tiny Tapeout experimental shuttle.

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A hardware engineer designed and taped out a 2×2 systolic array with JTAG debug infrastructure on GlobalFoundries 180nm in under two weeks through Tiny Tapeout's experimental shuttle. The project combined a matrix multiplication accelerator (using custom Booth Radix-4 multipliers) with in-silicon debug capabilities, operating across two clock domains. Despite severe I/O constraints and no SRAM availability, the design was validated through simulation, FPGA emulation with OpenOCD, and custom firmware on RP2040. The JTAG TAP includes custom instructions for probing internal registers, serving as proven IP for future tapeouts.

Two weeks until tapeout