Superconducting nanowire memory array achieves significantly lower error rate

MIT researchers developed a scalable superconducting nanowire memory array with a significantly lower error rate than previous designs. The 4×4 array uses nanowire loops with temperature-dependent switches and kinetic inductors to store data via magnetic flux. Operating at 1.3K, it achieves a bit error rate of 10⁻⁵ (1 error per 100,000 operations) and a functional density of 2.6 Mbit/cm². This advancement addresses key challenges in superconducting memory: scalability and error rates, bringing these energy-efficient components closer to practical deployment in quantum and low-energy computing systems.