A deep technical exploration of the 80386 processor's protection architecture, written as part of a series on building an 80386-compatible FPGA core in SystemVerilog. Covers the dedicated Protection Test Unit (a PLA with 148 product terms) that evaluates privilege rules in parallel rather than sequentially in microcode, the
•20m read time• From nand2mario.github.io
Table of contents
The protection problemA centralized protection unitMaking it generic: the PTSAV/PTOVRR callbackMaking it fast: 3-cycle delay slotsSpeeding up virtual memoryVirtual 8086 modeConclusionSort: