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Security researchers have discovered significant vulnerabilities in commercial RISC-V CPU implementations, challenging claims that the open-source ISA is inherently more secure than x86_64. Using RISCover, an open-source differential fuzzing framework, researchers found critical flaws including GhostWrite (a bug allowing unprivileged code to write directly to physical memory in T-Head's XuanTie C910) and denial-of-service vulnerabilities. The findings reveal that while RISC-V specifications provide strong security primitives, vendors consistently choose insecure defaults, enable unprivileged timing sources, ship undocumented extensions without validation, and omit speculation mitigations. Researchers warn these implementation decisions will be permanently embedded in billions of chips.

Security Researchers Find Current RISC-V CPU Implementations Coming Up Short