Hackaday

A deep dive into how the Intel 8087 FPU co-processor identifies and executes its instructions when sharing a bus with the 8086/8088 CPU. The mechanism relies on eight special ESCAPE opcodes reserved for the co-processor, with data sharing occurring through system memory via a BIU register. Instruction decoding is handled primarily by a microcode engine backed by a compact ROM with only 22 entry points, supplemented by logic gates and PLAs to keep silicon area manageable. The article highlights the clever engineering trade-offs made to implement complex floating-point operations like cosine within severe hardware constraints of the era.

How The Intel 8087 FPU Knows Which Instructions To Execute