Mid-circuit measurements used in quantum error correction are essential in the architecture of a fault-tolerant quantum computer, as they read out syndrome data and drive logic gates. Here, we use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic. First, we identify that idling errors occurring during readout periods are highly detrimental to a quantum memory. We demonstrate significant improvements to the memory by designing and implementing a low-depth syndrome extraction circuit. Second, we perform a stability experiment to investigate the type of failures that can occur during logic gates due to readout assignment errors. We find that the error rate of the stability experiment improves with additional stabilizer readout cycles, revealing a trade-off as additional stability comes at the expense of time over which the memory can decay. We corroborate our results using holistic device benchmarking and by comparison to numerical simulations. Finally, by varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates, with measurement noise playing a dominant role in logical gate performance. With rapid progress in quantum error correction, clear performance benchmarks are needed to assess readiness for fault tolerant operation. Here the authors report benchmarking and noise characterization in a superconducting quantum processor, identifying key factors that impact error-corrected logic.

Nature is a scientific journal publishing research articles, reviews, and commentary across a wide range of scientific disciplines. Readers can find articles on topics such as biology, chemistry, physics, and environmental science. Additionally, they can learn about  research, scientific discoveries, and advances in understanding the natural world.

Nature

Researchers investigate failure mechanisms in error-corrected quantum logic gates using a heavy-hex code on a superconducting qubit array. Key findings include: idling errors during readout periods are highly detrimental to quantum memory, and a low-depth syndrome extraction circuit significantly improves memory performance. A stability experiment reveals that additional stabilizer readout cycles improve error rates but introduce a trade-off with memory decay time. Numerical simulations identify measurement noise as the dominant factor impacting fault-tolerant logical gate fidelity, providing benchmarks for assessing readiness for fault-tolerant quantum operation.

Characterising the failure mechanisms of error-corrected quantum logic gates