Are Caches Accessed with a Virtual or Physical Address?

CPU caches can be addressed using virtual addresses, physical addresses, or a combination of both. Four cache addressing schemes exist: PIPT (physically indexed, physically tagged), VIVT (virtually indexed, virtually tagged), PIVT (physically indexed, virtually tagged), and VIPT (virtually indexed, physically tagged). PIPT is robust but slow due to mandatory address translation before cache access. VIVT is fast but suffers from homonym and aliasing problems requiring cache flushes on context switches. PIVT combines the worst of both worlds and is rarely used. VIPT is the modern standard, enabling parallel address translation via the MMU/TLB and cache set lookup using the page offset bits. This parallelism works because the page offset bits remain unchanged during translation. VIPT has constraints: the set index plus line offset bits must not exceed the page offset bits, which is why most L1 caches are limited to 32–64 KB.